The AdoredTV channel introduced a roadmap that escaped AMD and considerations its server processors. It additionally reveals the brand new SP6 slot or Genoa-X processors, which ought to get an prolonged L3 cache.
It’s, in fact, attainable that it is a hoax, however the leaked supplies don’t appear to be that, and we count on Lisa Su to be the long run EPYC server processors in a couple of days. It’s extra possible that it’s actually a part of her presentation, or quite the identical data that we be taught from her, however proven on some inner roadmap.
The primary slide reveals the person platforms divided by sockets, so we’ve got the well-known SP3 for the present Milan and Milan-X processors, however then the brand new SP5 and even SP6. We’ve not heard of SP6 but, and whereas SP5 is just the successor to SP3 for the Zen 4 era EPYC (Genoa and Bergamo), SP6 appears to be like like some weaker server processors (not essentially EPYC) that provide weaker tools in each method. It will likely be solely single-socket techniques with 32 Zen 4 cores or 64 weaker Zen 4c cores with a variety of 70 to 225W TDP. There may also be solely six reminiscence channels for DDR5 and fewer PCIe / CXL strains.
Moreover, the primary image revealed the era of Genoa-X, or the successor of at this time’s Milan-X. Like Zen 3, Zen 4 ought to have a capability of 4 MB of L3 cache per core, so it is no marvel that AMD will in all probability wish to provide variations with prolonged L3 cache. The query is whether or not, as within the case of Milan-X, it will likely be a complete of 96 MB L3 per chiplet, or maybe extra.